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datasheet 3.3 v/2.5 v 1:15 pecl/lvcmos clock fanout buffer MPC9449 nrnd MPC9449 revision 6 december 21, 2012 1 ?2012 integrated device technology, inc. the MPC9449 is a 3.3 v or 2.5 v compat ible, 1:15 clock fanout buffer targeted for high performance clock tree applicat ions. with output frequencies up to 200 mhz and output skews less than 200 ps the device meets the needs of the most demanding clock applications. features ? 15 lvcmos compatible clock outputs ? two selectable lvcmos and one diff erential lvpecl compatible clock inputs ? selectable output frequency divider (divide-by-one and divide-by-two) ? maximum clock frequency of 200 mhz ? maximum clock skew of 200 ps ? high-impedance output control ? 3.3 v or 2.5 v power supply ? drives up to 30 seri es terminated clock lines ? ambient temperature range ?40 ? c to +85 ? c ? 52-lead lqfp packaging, pb-free ? supports clock distribution in network ing, telecommunication and computing applications ? pin and function compatible to mpc949 functional description the MPC9449 is specifically designed to distribute lvcmos compatible clock signals up to a frequency of 200 mhz. the device has 15 identical outputs, organized in four output banks. each output bank provides a retimed or frequency divided copy of the input signal with a near zero skew. the output buffer supports driving of 50 ? terminated transmission lines on the incident edge: each output is capable of drivi ng either one parallel terminated or two series terminated transmission lines. two selectable lvcmos compatible clock inputs are available. this feature supports redundant di fferential clock sources. in addition, the MPC9449 accepts one differential pecl clock si gnal. the dselx pins choose between division of the input reference frequency by one or two. the frequency divider can be set individually for each of the four output banks. applying th e oe control will force the outp uts into high-impedance mode. all inputs have an internal pull-up or pull-down resistor preven ting unused and open inputs from floating. the device supports a 2.5 v or 3.3 v power supply and an ambient temperature range of ?40 ? c to +85 ? c. the MPC9449 is pin and function compatible but performance-enhanced to the mpc949. the device is packaged in a 52-lead lqfp package. 3.5 v/2.5 v 1:15 pecl/lvcmos clock fanout buffer ae suffix 52-lead lqfp package pb-free package case 848d-03 nrnd ? not recommend for new designs
package dimensions MPC9449 revision 6 december 21, 2012 2 ?2012 integrated device technology, inc. MPC9449 data sheet 3.3v/2.5v 1:15 pecl/lvcm os clock fanout buffer figure 1. MPC9449 logic diagram figure 2. pc9449 52-lead package pinout (top view) ? 2 ? 1 v cc v cc cclk0 cclk1 pclk pclk pclk_sel qa0 dselb dselc mr/oe dseld dsela qa1 qb0 qb1 qb2 qc0 qc1 qc2 qc3 qd0 qd1 qd2 qd3 qd4 qd5 cclk_sel 0 1 0 1 0 1 0 1 0 1 0 1 nc v cc qb2 gnd qb1 v cc qb0 gnd gnd qa1 v cc qa0 gnd nc v cc qd4 gnd qd3 v cc qd2 gnd qd1 v cc qd0 gnd nc nc gnd qc0 v cc qc1 gnd qc2 v cc qc3 gnd gnd qd5 nc cclk_sel mr/oe v cc cclk0 cclk1 pclk pclk pclk_sel dsela dselb dselc dseld gnd 40 41 42 43 44 45 46 47 48 49 50 51 52 25 24 23 22 21 20 19 18 17 16 15 14 12345678910111213 39 38 37 36 35 34 33 32 31 30 29 28 27 26 MPC9449
MPC9449 revision 6 december 21, 2012 3 ?2012 integrated device technology, inc. MPC9449 data sheet 3.3v/2.5v 1:15 pecl/lvcm os clock fanout buffer table 1. function table control default 0 1 pclk_sel 0 lvcmos clock input selected (cclk0 or cclk1) pclk differential input selected cclk_sel 0 cclk0 selected cclk1 selected dsela, dselb, dselc, dseld 0 0 0 0 ? 1 ? 2 mr/oe 1 outputs enabled outputs disabled (high impedance) table 2. pin configuration pin i/o type function pclk, pclk input lvpecl differential lvpecl clock input cclk0, cclk1 input lvcmos lvcmos clock inputs pclk_sel input lvcmos lvpecl clock input select cclk_sel input lvcmos lvcmos clock input select dsela, dselb, dselc, dseld input lvcmos clock divider selection mr/oe input lvcmos output enable/disable (high-impedance tristate) qa0-1, qb0-2, qc0-3, qd0-5 output lvcmos clock outputs gnd supply ground negative power supply (gnd) v cc supply v cc positive power supply for i/o and core. all v cc pins must be connected to the positive power supply for correct operation table 3. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc ? 2v mm esd protection (machine model) 200 v hbm esd protection (human body model) 2000 v lu latch-up immunity 200 ma c pd power dissipation capacitance 12 pf per output c in input capacitance 4.0 pf inputs table 4. absolute maximum ratings (1) 1. absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. exposure to these conditions or conditions beyond t hose indicated may adversely affect device reliabi lity. functional operat ion at absolute-maxim um-rated conditions is not implied. symbol characteristics min max unit condition v cc supply voltage ?0.3 3.8 v v in dc input voltage ?0.3 v cc ? 0.3 v v out dc output voltage ?0.3 v cc ? 0.3 v i in dc input current ? 20 ma i out dc output current ? 50 ma t s storage temperature ?65 125 ? c
MPC9449 revision 6 december 21, 2012 4 ?2012 integrated device technology, inc. MPC9449 data sheet 3.3v/2.5v 1:15 pecl/lvcm os clock fanout buffer table 5. dc characteristics (v cc = 3.3 v 5%, t a = ?40 ? c to 85c) symbol characteristics min typ max unit condition v ih input high voltage 2.0 v cc ? 0.3 v lvcmos v il input low voltage 0.8 v lvcmos v oh output high voltage 2.4 v i oh = ?24 ma (1) 1. the MPC9449 is capable of driving 50 ? transmission lines on the incident edge. each output drives one 50 ? parallel terminated transmission line to a te rmination voltage of v tt . alternatively, the device drives up to two 50 ? series terminated transmission lines. v pp peak-to-peak input voltage pclk, pclk 250 mv lvpecl v cmr (2) 2. v cmr (dc) is the crosspoint of the differential input signal. func tional operation is obtained when the crosspoint is within the v cmr range and the input swing lies within the v pp (dc) specification. common mode range pclk, pclk 1.0 v cc ?0.6 v lvpecl v ol output low voltage 0.55 0.30 v v i ol = 24 ma i ol = 12 ma z out output impedance 14 ? 17 ? i in input current ? 200 ? av in = v cc or gnd i ccq maximum quiescent supply current 10 ma all v cc pins table 6. ac characteristics (v cc = 3.3 v 5%, t a = ?40 ? c to 85c) (1) 1. ac characteristics apply for parallel output termination of 50 ? to v tt . symbol characteristics min typ max unit condition v pp peak-to-peak input voltage pclk, pclk 400 1000 mv lvpecl v cmr (2) 2. v cmr (ac) is the crosspoint of the differential input signal. norm al ac operation is obtained when t he crosspoint is within the v cmr range and the input swing lies within the v pp (ac) specification. violation of v cmr or v pp impacts propagation delay. common mode range pclk, pclk 1.0 v cc ?0.6 v lvpecl f max output frequency 0 200 mhz f ref input frequency 0 200 mhz t p, ref reference input pulse width 1.5 ns t r , t f cclk0, cclk1 input rise/fall time 1.0 ns 0.8 to 2.0 v t sk(o) output-to-output skew qa outputs qb outputs qc outputs qd outputs same frequency all outputs different frequencies all outputs 50 50 50 100 200 300 ps ps ps ps ps ps t sk(pp) device-to-device skew 2.5 ns t sk(p) output pulse skew 250 ps dc ref = 50% t plh , hl propagation delay cclk0 or cclk1 to any q pclk to any q 1.0 1.0 3.0 3.0 5.0 5.0 ns ns t plz, hz output disable time oe to any q 11 ns t pzl, lz output enable time oe to any q 11 ns t r , t f output rise/fall time (3) 3. an input rise/fall time greater than that specified may be used, but ac characteristics are not guaranteed under such a condi tion. 0.1 1.0 ns 0.55 to 2.4 v t jit(cc) cycle-to-cycle jitter rms (1 ? )tbd ps
MPC9449 revision 6 december 21, 2012 5 ?2012 integrated device technology, inc. MPC9449 data sheet 3.3v/2.5v 1:15 pecl/lvcm os clock fanout buffer table 7. dc characteristics (v cc = 2.5 v 5%, t a = ?40 ? c to 85c) symbol characteristics min typ max unit condition v ih input high voltage 1.7 v cc ? 0.3 v lvcmos v il input low voltage ?0.3 0.7 v lvcmos v pp peak-to-peak input voltage pclk, pclk 250 mv lvpecl v cmr (1) 1. v cmr (dc) is the crosspoint of the differential input signal. func tional operation is obtained when the crosspoint is within the v cmr range and the input swing lies within the v pp (dc) specification. common mode range pclk, pclk 1.0 v cc ?0.6 v lvpecl v oh output high voltage 1.8 v i oh = ?15 ma (2) 2. the MPC9449 is capable of driving 50 ? transmission lines on the incident edge. each output drives one 50 ? parallel terminated transmission line to a te rmination voltage of v tt . v ol output low voltage 0.6 v i ol = 15 ma z out output impedance 17?20 ? i in input current (3) 3. inputs have pull-down or pull-up resistors affecting the input current. ? 200 ? av in = v cc or gnd i cc maximum quiescent supply current 10 ma all v cc pins table 8. ac characteristics (v cc = 2.5 v 5%, t a = -40 ? c to 85c) (1) 1. ac characteristics apply for parallel output termination of 50 ? to v tt . symbol characteristics min typ max unit condition v pp peak-to-peak input voltage pclk, pclk 400 1000 mv lvpecl v cmr (2) 2. v cmr (ac) is the crosspoint of the differential input signal. norm al ac operation is obtained when t he crosspoint is within the v cmr range and the input swing lies within the v pp (ac) specification. violation of v cmr or v pp impacts propagation delay. common mode range pclk, pclk 1.2 v cc ?0.6 v lvpecl f max output frequency 0 200 mhz f ref input frequency 0 200 mhz t p, ref reference input pulse width 1.5 ns tr, tf cclk input rise/fall time 1.0 ns 0.7 to 1.7 v t sk(o) output-to-output skew qa outputs qb outputs qc outputs qd outputs same frequency all outputs different frequencies all outputs 50 50 50 100 200 300 ps ps ps ps ps ps t sk(pp) device-to-device skew 5.0 ns t sk(p) output pulse skew 350 ps dc ref = 50% t plh, hl propagation delay cclk0 or cclk1 to any q pclk to any q 1.0 1.0 3.5 3.5 7.0 7.0 ns ns t plz, hz output disable time oe to any q 11 ns t pzl, lz output enable time oe to any q 11 ns t r , t f output rise/fall time (3) 3. an input rise/fall time greater than that specified may be used, but ac characteristics are not guaranteed under such a condi tion. 0.1 1.0 ns 0.6 to 1.8 v t jit(cc) cycle-to-cycle jitter rms (1 ? )tbd ps
MPC9449 revision 6 december 21, 2012 6 ?2012 integrated device technology, inc. MPC9449 data sheet 3.3v/2.5v 1:15 pecl/lvcm os clock fanout buffer applications information driving transmission lines the MPC9449 clock driver was designed to drive high speed signals in a terminated transmission line environment. to provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. with an output impedance of less than 20 ? the drivers can drive either para llel or series terminated transmission lines. for more information on transmission lines the reader is referred to freescale semiconductor application note an1091. in most high performance clock networks point-to-point distribution of signals is the method of choice. in a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. the parallel technique terminates the signal at the end of the line with a 50 ? resistance to v cc ? 2. this technique draws a fairly high level of dc current and thus only a single terminated line can be driven by each output of the MPC9449 clock driver. for the series terminated case however there is no dc current draw, thus the outputs can drive multiple series terminated lines. figure 3 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. when taken to its extreme the fanout of the MPC9449 clock driver is effectively doubled due to its capability to drive multiple lines. figure 3. single versus dual transmission lines the waveform plots in figure 4 show the simulation results of an output driving a single line versus two lines. in both cases the drive capability of the MPC9449 output buffer is more than sufficient to drive 50 ? transmission lines on the incident edge. note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. this suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the mp c9449. the output waveform in figure 4 shows a step in the wavefo rm, this step is caused by the impedance mismatch seen looking into the driver. the parallel combination of the 36 ? series resistor plus the output impedance does not matc h the parallel combination of the line impedances. the voltage wave launched down the two lines will equal: v l =v s (z 0 ? (r s + r 0 + z 0 )) z 0 = 50 ? || 50 ? r s = 36 ? || 36 ? r 0 = 14 ? v l = 3.0 (25 ? (18 + 17 + 25) = 1.31 v at the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 v. it will then increment towards the quiescent 3.0 v in steps separated by one round trip delay (in this case 4.0 ns). 1. final skew data pending specification. figure 4. single versus dual waveforms since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflec tions on the line. to better match the impedances when driving multiple lines the situation in figure 5 should be used. in this case the series terminating resistors are reduced such that when the parallel combination is added to the ou tput buffer impedance the line impedance is perfectly matched. figure 5. optimized dual line termination 14 ? in MPC9449 output buffer r s = 36 ? z o = 50 ? outa 14 ? in MPC9449 output buffer r s = 36 ? z o = 50 ? outb0 r s = 36 ? z o = 50 ? outb1 time (ns) voltage (v) 3.0 2.5 2.0 1.5 1.0 0.5 0 2 4 6 8 101214 outb t d = 3.9386 outa t d = 3.8956 in 14 ? MPC9449 output buffer r s = 22 ? z o = 50 ? r s = 22 ? z o = 50 ? 14 ? + 22 ? || 22 ? = 50 ? || 50 ? 25 ? = 25 ?
MPC9449 revision 6 december 21, 2012 7 ?2012 integrated device technology, inc. MPC9449 data sheet 3.3v/2.5v 1:15 pecl/lvcm os clock fanout buffer figure 6. cclk MPC9449 ac test reference for v cc = 3.3 v and v cc = 2.5 v figure 7. pclk MPC9449 ac test reference pulse generator z = 50 ? r t = 50 ? z o = 50 ? r t = 50 ? z o = 50 ? MPC9449 dut v tt v tt differential pulse generator z = 50 ? r t = 50 ? z o = 50 ? r t = 50 ? z o = 50 ? MPC9449 dut v tt v tt
MPC9449 revision 6 december 21, 2012 8 ?2012 integrated device technology, inc. MPC9449 data sheet 3.3v/2.5v 1:15 pecl/lvcm os clock fanout buffer figure 8. output-to-output skew t sk(o) figure 9. propagation delay (t pd ) test reference figure 10. propagation delay (t pd ) test reference figure 11. propagation delay t sk(p) test reference figure 12. output transition time test reference figure 13. cycle-to-cycle jitter figure 14 the pin-to-pin skew is defined as the wo rst case difference in propagation delay be- tween any similar delay path within a single device v cc v cc 2 gnd v cc v cc 2 gnd t sk(o) v cc v cc 2 gnd t (lh) q x cclk v cc v pp t (hl) v cc 2 gnd v cc v cc 2 gnd t (lh) q x pclk v pp t (hl) v cmr pclk v cc v cc 2 gnd t (lh) q x cclk v cc t (hl) v cc 2 gnd t (hl) t sk(p) = ? t plh ?t plh ? t f t r v cc =3.3 v v cc =2.5 v 2.4 1.8 v 0.55 0.6 v the variation in cycle time of a sig nal between adjacent cycles, over a ran- dom sample of adjacent cycle pairs t n t jit(cc) = |t n -t n+1 | t n+1
MPC9449 revision 6 december 21, 2012 9 ?2012 integrated device technology, inc. MPC9449 data sheet 3.3v/2.5v 1:15 pecl/lvcm os clock fanout buffer date 11/15/94 case 848d-03 issue d notes: 1. 2. 3. 4. 5. 6. 7. controlling dimensions: millimeter. dimensioning and tolerancing per ansi y14.5m, 1982. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. datums -l-, -m- and -n- to be determined at datum plane -h-. dimensions s and v to be determined at seating plane -t-. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.46 (0.018). minimum space between protrusion and adjacent lead or protrustion 0.07 (0.003). f section ab-ab rotated 90? clockwise s l-m m 0.13 (0.005) n s t plating base metal d j u s 0.05 (0.002) 0.25 (0.010) gage plane c2 c1 w k e z 1 view aa 2x r r1 1 13 14 26 27 39 40 52 4x 13 tips 4x n 0.20 (0.008) h l-m n 0.20 (0.008) t l-m b v b1 a s v1 a1 s1 -l- -n- -m- 3x view y view aa seating plane c 0.10 (0.004) t 4x 3 4x 2 -h- -t- dim a a1 b b1 c c1 c2 d e f g j k r1 s s1 u v v1 w z 1 3 2 min --- 0.05 1.30 0.20 0.45 0.22 0.07 0.08 0.09 0? 0? min --- 0.002 0.051 0.008 0.009 0.018 0.003 0.003 0.004 0? 0? max 1.70 0.20 1.50 0.40 0.35 0.75 0.20 0.20 0.16 7? --- max 0.067 0.008 0.059 0.016 0.030 0.014 0.008 0.008 0.006 7? --- millimeters 10.00 bsc 5.00 bsc 10.00 bsc 5.00 bsc 0.65 bsc 0.50 ref 12.00 bsc 6.00 bsc 12.00 bsc 6.00 bsc 0.20 ref 1.00 ref 12? ref 12? ref inches 0.394 bsc 0.197 bsc 0.394 bsc 0.197 bsc 0.026 bsc 0.020 ref 0.472 bsc 0.236 bsc 0.472 bsc 0.236 bsc 0.008 ref 0.039 ref 12? ref 12? ref ab ab view y c l -x- x=l, m, n g package dimensions case 848d-03 issue d 52-lead lqfp package
MPC9449 revision 6 december 21, 2012 10 ?2012 integrated device technology, inc. MPC9449 data sheet 3.3v/2.5v 1:15 pecl/lvcm os clock fanout buffer revision history sheet rev table page description of change date 6 1 nrnd ? not recommend for new designs 12/21/12
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2012. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution MPC9449 data sheet 3.3v/2.5v 1:15 pecl/lvcm os clock fanout buffer

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